Status byte register

The status byte register stores STB and RQS (MSS) messages as defined by the IEEE488.1 standard. The status byte register can be read using IEEE488.1 serial polling or IEEE488.2 common command *STB?.

When serial polling is carried out, bit 6 responds with the request service (RQS). The status byte value is not changed by serial polling.

*STB? makes the device transmit the contents of the status byte register and the master status summary (MSS) message.

*STB? does not change the status byte, MSS, and RQS.

Table 4 Status byte register

Bit | Bit Weight | Bit Name | Description
0 | 1 | Reserved | Reserved for future use by the IEEE488. The bit value is notified as zero.
1 | 2 | Reserved
2 | 4 | Error/Event Queue | If data exists in the error or event queue, this bit is set to true.
3 | 8 | Questionable Status Register (QUES) | This bit is set to true when a bit is set in the QUEStionable event status register and the corresponding bit in the QUEStionable status enable register is true.
4 | 16 | Message Available (MAV) | This bit is set to true when a request is received from the digital programming interface and the KFM2151 is ready to output the data byte.
5 | 32 | Standard Event Status Bit Summary (ESB) | This bit is set to true when a bit is set in the event status register.
6 | 64 | Request Service (RQS) | This bit is set to true when a bit is set in the service request enable register, and the corresponding bit exists in the status byte.
Master Status Summary (MSS) | Set by one of the following: Status byte bit 0 and service request enable register bit 0. Status byte bit 1 and service request enable register bit 1. Status byte bit 2 and service request enable register bit 2. Status byte bit 3 and service request enable register bit 3. Status byte bit 4 and service request enable register bit 4. Status byte bit 5 and service request enable register bit 5. Status byte bit 7 and service request enable register bit 7.
7 | 128 | Operation Status Register (OPER) | This bit is set to true when a bit is set in the OPERation event status register and the corresponding bit in the OPERation status enable register is set.
8-15 |  | Not Used | Not Used